General Purpose, Low Power Supercomputing Using Reconfiguration
Google engEDU
56 min – Feb 28, 2006
Google TechTalks
February 28, 2006
Prof. Bob Brodersen
ABSTRACT:
The ability of FPGA technology to exploit the advances in IC fabrication technology has resulted in the present situation in which a FPGA computing fabric is the most power and area efficient approach for general purpose parallel computing. This has occurred because the Von-Neumann processor architectures are now power limited and can no longer fully exploit the technology advances (thus the move to multi-cores). Hardware composed of arrays of FPGA’s and memory has been design that achieves a TeraOp/second of performance per board with over an order of magnitude higher efficiency for the computation per unit power over conventional microprocessors. To achieve these results, however, requires a high level of parallelism in the application program, which is typically not exposed in sequential programming languages. Even worse for application programmers, has been the low level of abstraction of FPGA hardware, which requires the user to be a hardware expert. It is believed that for any application that can be parallelized and streamed will presently achieve orders of magnitude speed-up for the same power and cost and even more importantly will have a power efficiency which will improve exponentially in each subsequent IC technology node.
video
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